November 29, 2021

Generate SINE waveforms with CORDIC IP

Second, custom XILINX CORDIC IP

Take ISE10.1 software as an example. The integrated CORDIC algorithm IP is V3.0. The specific steps are as follows:
1. Create a new project, click NEW Source... to call IP Core Generator, enter the module name as MyCordic and press NEXT
2. Select the CORDIC algorithm IP on the Select IP page as shown below:


3. Click NEXT to enter the first page of the IP configuration interface, as shown below:


Here we choose Sin and Cos as the function selection, others are the default.
4. After NEXT, enter the second page of the IP configuration interface, as shown below:


Here the Phase Format we chose Scaled Radians. and removed the CE foot.
In the Phase Format, the Radians unit is radians, and the Scaled Radians unit is how many radians.
5. After NEXT, enter the third page of the IP configuration interface, as shown below:


According to the accuracy of the D/A device, we can select the 12-bit width for the input and output, and the others are the default values.
6, after NEXT, enter the fourth page of the IP configuration interface, as shown below:


In Advanced ConfiguraTIon Parameters, IteraTIons specifies the number of internal iterations. If 0 is specified, the number of iterations is automatically selected based on the selected precision. Precision specifies the internal iteration plus or minus precision. If specified as 0, the iteration precision is automatically selected based on the bit width of the selected input and output.
Coarse RotaTIon is used to extend the phase to the entire coordinate plane. If you do not check the front of it, the input phase is limited to -PI/4~PI/4. We must use this function when generating sinusoidal waveforms. Check the previous one.
7. Finally, the Generate in the lower left corner generates the IP. Explain the IP pin function:
PHASE_IN: Phase of the input.
CLK: input clock
X_OUT: output cosine value
Y_OUT: output sine value
RDY: The data ready signal, when there is new data, outputs a high level pulse in the first clock cycle RDY.
8. Finally, we need a top-level module to call CORDIC IP and write it to the LTC2624 DAC device on the Xilinx Spartan?-3E FPGA Starter Kit development board via the SPI bus. We can modify it based on Xilinx's DEMO s3esk_picoblaze_dac_control. , add the relevant code to the project, instantiate the CORDIC IP, modify the Picoblaze program, etc., the detailed steps are omitted.
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