September 28, 2020

MIPS latest Aptiv three series of deep analysis

Recently, MIPS introduced the ApTIv microprocessor core of its latest generation of licensable IP cores, including proApTIv, interApTIv and microApTIv, which are designed to provide differentiated and sophisticated performance for high- and low-end application markets and emerging market expansion. Level. Mr. He Yingwei, General Manager of MIPS Technologies Shanghai explained that the new product was named Aptiv and was designed to express the lively, competent and efficient nature of the processor. At the same time, it has a significantly differentiated product branch, and it also prepares for the long-term needs of different market needs.

Aptiv three series of deep analysis

proAptiv - the most outstanding multi-core IP series

The proAptiv processor delivers the highest performance in the entire Aptiv family and is a high-end processor for high-end smartphones and connected consumer electronics applications such as tablets and home entertainment. Up to 6 cores can work together to meet some of the most demanding requirements in network applications. In Coremark's latest evaluation, it scored 4.4, which is 60%-75% higher than the MIPS traditional 1074K series, and is nearly 50% higher than the current ARM ARM9 with a maximum score of 2.88. At the same time, the area is reduced by half compared with the Cortex A15, which has not yet announced the Coremark score. This means that on the same silicon area as the A15 dual-core processor, proAptiv can add up to 1MB of L2 cache or integrate 4 proAptiv cores while integrating the two cores.

It is worth mentioning that in the basic kernel architecture of proAptiv, the super-scalar out-of-order of 3 launches has a significant advantage over the mainstream dual-issue superscalar. At the same time, the floating-point unit is placed in the internal pipeline of the CPU, which is the first of its kind. Above, we can easily feel the proAptiv's performance, efficiency and low cost and the substantial increase and violent counterattack.

proAptiv basic kernel architecture

——interAptiv: Efficient multi-core IP series that solves the contradiction between function and performance with multi-threading

interAptiv is a smaller processor with a smaller circuit size and power consumption than proAptiv, which is intended for use in mainstream set-top boxes, mid-range mobile, home entertainment products.

In fact, multi-threaded applications are much earlier than multicore. At the end of 2010, ARM proposed a plan to add multi-threading technology to processors to improve performance. As an interAptiv with multi-threading technology added to multi-core systems, it compares with the Cortex-A15 processor that does not support multi-threading. Shows more room for performance improvement. In addition, its evaluation score in Coremark has increased by nearly 50% compared to similar products such as Cortex A9.

interAptiv basic kernel architecture

——microAptiv: DSP application expansion achieves compact and accurate core IP series

The microAptiv processor was born for high-speed signal processing for cost-sensitive MCU/embedded applications. Its biggest feature is its compactness and efficiency. These are derived from the MIPS team in Shanghai, China, which has created a micromips instruction set and DSP unit. Now microAptiv is available and offers Cache/MMU or Cache version selection. Very exciting is the Cache/MMU version of microAptiv, which runs on large operating systems such as Android and Linux.

When interviewing Mr. He Yingwei, the general manager of MIPS Technologies in Shanghai, China, he said that the development of all microAptiv series was completed by MIPS' R&D team in Shanghai. While the Shanghai team continues to grow, there are already two customers ready to choose the micro core for the development of MCU products. It is very exciting to see their information and the final shape and release of the product.

microAptiv MPU core features

See how MIPS can achieve differentiated competition and counterattack

Mr. Fei Zheping, Marketing Director of MIPS China, said at the recent Aptiv new product launch conference that the experimental data shows that the latest Aptiv series is not only greatly improved compared with the traditional MIPS processor, but also compared with ARM and other companies. Similar products have great advantages and continuous development space. Fei Zheping, who has 7 years of engineering experience in ARM, uses the ARM command to concentrate on the advantages and disadvantages of the coexistence. This explains and explains why the MIPS instruction set is more pure and concise. It is also because MIPS has a more compatible instruction set, which makes the MIPS classic series continue to be in the market, and has achieved good compatibility with Aptiv.

At the same time, he also said that the release of new MIPS products will have little pressure on the entire ecosystem. Because it has very complete binary compatibility, the upgrades required for his partners and tool vendors for new products are almost zero.

MIPS in China

Compared with many other semiconductor manufacturers, MIPS' investment in the Chinese market is very positive and characteristic. From MIPS and Junzheng to release Android4.0 tablet PC, the microAptiv series of research and development is completed by MIPS Technology Shanghai team. MIPS not only drives the transformation of China's processor market from production to R&D, but also greatly enhances the MIPS core in China. Influence and technical credibility. This is indeed a wise strategy.


All Aptiv kernels can be licensed starting today. The proAptiv family supports a wide range of features and performance combinations in both single-core and multi-core versions and is expected to be available in mid-2012. The new proAptiv FPU is also available now. The interAptiv series will also be available in mid-2012 with dual-core and quad-core configurations and FPU options. The single-core version will be available in the fourth quarter. The microAptiv series is available now with Cache/MMU or Cache version options.

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